1. Field of the Invention
The present invention relates to an electrically programmable nonvolatile semiconductor memory device (EEPROM) and, more particularly, to an EEPROM for performing a multivalue storing operation for storing information of two or more bits in one memory cell.
2. Description of the Related Art
As one of EEPROMs, a NAND EEPROM which can be integrated at a high density is known. In this NAND EEPROM, a plurality of memory cells are connected in series with each other as one unit such that adjacent memory cells have a source and a drain in common, and these memory cells are connected to a bit line. A memory cell generally has an FETMOS structure in which a charge accumulation layer and a control gate are stacked. A memory cell array is integrated and formed in a p-type well formed in a p- or n-type substrate. The drain side of a NAND cell is connected to a bit line through a selection gate, and the source side is connected to a common source line through a selection gate. The control gates of memory cells are continuously arranged in a row direction to form a word line.
The operation of this NAND-cell EEPROM is as follows. A data write operation is sequentially performed from a memory cell at a position farthest from the bit line. A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate voltage Vppm (=about 10 V) is applied to the control gate and selection gate of a memory cell closer to the bit line than the selected memory cell, and a voltage of 0 V or an intermediate voltage Vm (=about 8 V) is applied to the bit line in accordance with data. When the voltage of 0 V is applied to the bit line, the potential of the bit line is transferred to the drain of the selected memory cell, and electrons are injected into the charge accumulation layer of the selected memory cell. In this case, the threshold voltage of the selected memory cell is positively shifted. This state is represented by, e.g., “1”. When the voltage Vm is applied to the bit line, electrons are not effectively injected into the charge accumulation layer of the selected memory cell, and, therefore, the threshold voltage of the selected memory cell is kept negative without being changed. This state is an erased state, and is represented by “0”. A data write operation is performed to memory cells which share a control gate at once.
A data erase operation is performed to all the memory cells in a NAND cell at once. More specifically, all the control gates are set to be 0 V, and the p-type well is set to be 20 V. At this time, the selection gate, the bit line, and the source line are set to be 20 V. In this manner, electrons are discharged from the charge accumulation layers of all the memory cells into the p-type well, and the threshold voltages of the memory cells are negatively shifted.
A data read operation is performed as follows. That is, the control gate of a selected memory cell is set to be 0 V, the control gates and selection gates of the remaining memory cells are set to be a power supply potential Vcc (e.g., 5 V), and it is detected whether a current flows in the selected memory cell. Due to restrictions of the read operation, a threshold voltage set upon a “1”-data write operation must be controlled to fall within a range of 0 V to Vcc. For this purpose, a write verify operation is performed to detect only a memory cell in which data “1” is not sufficiently written, and rewritten data is set such that a rewrite operation is performed to only the memory cell in which data “1” is not sufficiently written (bit-by-bit verify operation). The memory cell in which data “1” is not sufficiently written is detected by performing a read operation (verify read operation) such that a selected control gate is set to be, e.g., 0.5 V (verify voltage).
More specifically, when the threshold voltage of the memory cell has a margin with respect to 0 V and is not set to be 0.5 V or more, a current flows in the selected memory cell, and the selected memory cell is detected as a memory cell in which data “1” is not sufficiently written. Since a current flows in a memory cell set to be a “0”-data-written state, a circuit called a verify circuit for compensating the current flowing in the memory cell is arranged to prevent the memory cell from being erroneously recognized as a memory cell in which data “1” is not sufficiently written. This verify circuit executes a write verify operation at a high speed. When a data write operation is performed while a write operation and a write verify operation are repeated, a write time for each memory cell is made optimum, and the threshold voltage of each memory cell set upon a “1”-data write operation is controlled to fall within a range of 0 V to Vcc.
In this NAND-cell EEPROM, in order to realize a multivalue storing operation, for example, it is considered that states set upon a write operation are set to be three states represented by “0”, “1”, and “2”. A “0”-data-written state is defined as a state wherein the threshold voltage is negative, a “1”-data-written state is defined as a state wherein the threshold voltage ranges from 0 V to ½ Vcc, and a “2”-data-written state is defined as a state wherein the threshold voltage ranges from ½ Vcc to Vcc. In a conventional verify circuit, a memory cell set to be a “0”-data written state can be prevented from being erroneously recognized as a memory cell in which data “1” or “2” is not sufficiently written.
However, the conventional verify circuit is not designed for a multivalue storing operation. For this reason, assuming that a memory cell set to be a data “2”-written state has a threshold voltage equal to or higher than a verify voltage for detecting whether data “1” is not sufficiently written and equal to or lower than ½ Vcc, when it is to be detected whether data “1” is not sufficiently written, no current flows in the memory cell, and the memory cell is erroneously recognized as a memory cell in which data “2” is sufficiently written.
In addition, in order to prevent erroneous recognition of a memory cell in which data is not sufficiently written and to perform a multivalue write verify operation, a verify write operation is performed to set a memory cell, in which data “1” is sufficiently written, in a “2”-data-written state, by detecting whether the memory cell is a memory cell in which data “2” is not sufficiently written. However, in this case, a memory cell set to be a “2”-data-written state is set in a “1”-data-written state at first and is then set in a “2”-data-written state. For this reason, a longer time is required for the write operation, and the write operation cannot be performed at a high speed.
As described above, when a conventional NAND-cell EEPROM is used for performing a multivalue storing operation, and a bit-by-bit verify operation is performed by a conventional verify circuit, an erroneous verify operation is disadvantageously performed.